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» Optimal module and voltage assignment for low-power
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ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
13 years 11 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
ICCAD
2003
IEEE
149views Hardware» more  ICCAD 2003»
14 years 1 months ago
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module L
This paper proposes an optimum methodology for assigning supply and threshold voltages to modules in a CMOS circuit such that the overall energy consumption is minimized for a giv...
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhij...
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Voltage Island Generation under Performance Requirement for SoC Designs
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...
Wai-Kei Mak, Jr-Wei Chen
DAC
2005
ACM
13 years 6 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
ICCAD
2008
IEEE
122views Hardware» more  ICCAD 2008»
14 years 1 months ago
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
Qiang Ma, Evangeline F. Y. Young