5 search results - page 1 / 1 » Optimal voltage testing for physically-based faults |
VTS
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
ISLPED
2006
ACM
13 years 11 months ago
2006
ACM
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...