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GLVLSI
2005
IEEE
205views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Optimization objectives and models of variation for statistical gate sizing
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
Matthew R. Guthaus, Natesan Venkateswaran, Vladimi...
TVLSI
2008
176views more  TVLSI 2008»
13 years 4 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 1 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
DATE
2000
IEEE
85views Hardware» more  DATE 2000»
13 years 9 months ago
Gate Sizing Using a Statistical Delay Model
This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used al...
E. T. A. F. Jacobs, Michel R. C. M. Berkelaar
PATMOS
2007
Springer
13 years 10 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...