Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing process...
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...