6 search results - page 1 / 2 » Optimization of VDD and VTH for low-power and high speed app... |
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
ISVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
GLVLSI
2008
IEEE
2008
IEEE
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
13 years 5 months ago
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
— In this paper, we present two designs for CMOS comparators: one which is targeted for high-speed applications and another for low-power applications. Additionally, we present h...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...