Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

9

ASPDAC
2000
ACM

favoriteEmaildiscussreport

95views Hardware» more ASPDAC 2000»

Optimization of VDD and VTH for low-power and high speed applications

13 years 9 months ago

Optimization of VDD and VTH for low-power and high speed applications

Download lowpower.iis.u-tokyo.ac.jp

Koichi Nose, Takayasu Sakurai

Real-time Traffic

ASPDAC 2000 | Hardware |

claim paper

Related Content

» Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits

» Simultaneous optimization of memory configuration and code allocation for low power embedd...

» CMOS Comparators for HighSpeed and LowPower Applications

» Exploring highspeed lowpower hybrid arithmetic units at scaled supply and adaptive clockst...

» Minimizing leakage What if every gate could have its individual threshold voltage

Post Info
More Details (n/a)

Added	01 Aug 2010
Updated	01 Aug 2010
Type	Conference
Year	2000
Where	ASPDAC
Authors	Koichi Nose, Takayasu Sakurai

Comments (0)