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ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
13 years 11 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
ISLPED
2004
ACM
102views Hardware» more  ISLPED 2004»
13 years 10 months ago
Microarchitectural power modeling techniques for deep sub-micron microprocessors
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M...
ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
13 years 11 months ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
TVLSI
1998
99views more  TVLSI 1998»
13 years 5 months ago
Some experiments about wave pipelining on FPGA's
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
Eduardo I. Boemo, Sergio López-Buedo, Juan ...