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DATE
2009
IEEE
120views Hardware» more  DATE 2009»
13 years 11 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
ISSS
1996
IEEE
114views Hardware» more  ISSS 1996»
13 years 8 months ago
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
In this paper we present the problem of flow graph balancing for minimizingthe required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cy...
Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, ...
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
13 years 11 months ago
Latency Minimization for Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) are a very useful means for modeling and analyzing streaming applications. Some performance indicators, such as throughput, have been studied b...
Amir Hossein Ghamarian, Sander Stuijk, Twan Basten...
ASPDAC
1999
ACM
157views Hardware» more  ASPDAC 1999»
13 years 9 months ago
A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization
: This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow gr...
Birger Landwehr
IPPS
2007
IEEE
13 years 11 months ago
C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for thes...
Najeem Lawal, Mattias O'Nils, Benny Thörnberg