954 search results - page 2 / 191 » Optimizing power and performance for reliable on-chip networ... |
TC
2008
13 years 5 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
NOCS
2008
IEEE
14 years 4 days ago
2008
IEEE
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...