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ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
14 years 2 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...
IEEEPACT
2008
IEEE
14 years 5 days ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
EUROPAR
2008
Springer
13 years 7 months ago
Compile-Time and Run-Time Issues in an Auto-Parallelisation System for the Cell BE Processor
Abstract. We describe compiler and run-time optimisations for effective autoparallelisation of C++ programs on the Cell BE architecture. Auto-parallelisation is made easier by anno...
Alastair F. Donaldson, Paul Keir, Anton Lokhmotov
ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
13 years 10 months ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
MICRO
2006
IEEE
105views Hardware» more  MICRO 2006»
13 years 11 months ago
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Rob...