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» Parametric Fault Simulation and Test Vector Generation
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DATE
2000
IEEE
136views Hardware» more  DATE 2000»
13 years 9 months ago
Parametric Fault Simulation and Test Vector Generation
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
Khaled Saab, Naim Ben Hamida, Bozena Kaminska
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
13 years 10 months ago
Test Vector Generation Based on Correlation Model for Ratio-Iddq
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
14 years 5 months ago
Spectral RTL Test Generation for Microprocessors
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Nitin Yogi, Vishwani D. Agrawal
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
13 years 9 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik
ET
2006
120views more  ET 2006»
13 years 4 months ago
Automatic Test Pattern Generation for Resistive Bridging Faults
An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced s...
Piet Engelke, Ilia Polian, Michel Renovell, Bernd ...