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ASPDAC
2011
ACM
227views Hardware» more  ASPDAC 2011»
12 years 9 months ago
Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph
– This paper concerns throughput-constrained parallel execution of synchronous data flow graphs. This paper assumes static mapping and dynamic scheduling of nodes, which has seve...
Tae-ho Shin, Hyunok Oh, Soonhoi Ha
SODA
2010
ACM
205views Algorithms» more  SODA 2010»
14 years 3 months ago
Maximum Flows and Parametric Shortest Paths in Planar Graphs
We observe that the classical maximum flow problem in any directed planar graph G can be reformulated as a parametric shortest path problem in the oriented dual graph G . This ref...
Jeff Erickson
SAC
2010
ACM
13 years 10 months ago
An algorithm to generate the context-sensitive synchronized control flow graph
The verification of industrial systems specified with CSP often implies the analysis of many concurrent and synchronized components. The cost associated to these analyses is usu...
Marisa Llorens, Javier Oliver, Josep Silva, Salvad...
ARC
2010
Springer
167views Hardware» more  ARC 2010»
13 years 9 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
Kunjan Patel, Chris J. Bleakley
VLSISP
2008
111views more  VLSISP 2008»
13 years 5 months ago
Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Abstract. In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound ...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede