4 search results - page 1 / 1 » Parasitic Aware Process Variation Tolerant Voltage Controlle... |
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...
GLVLSI
2009
IEEE
13 years 8 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
— A new oscillator sensitivity analysis that predicts the impact of parameter variations of a VCO in a PLL is presented in this paper. Sensitivities of an oscillator’s steady-s...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...