24 search results - page 2 / 5 » Partial Error Masking to Reduce Soft Error Failure Rate in L... |
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
DSN
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
— A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates...
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...