23 search results - page 3 / 5 » Partial scan delay fault testing of asynchronous circuits |
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
TCAD
2011
13 years 7 days ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
ICCD
2006
IEEE
13 years 11 months ago
2006
IEEE
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...