35 search results - page 1 / 7 » Pattern generation for a deterministic BIST scheme |
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It take...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
ET
2000
13 years 4 months ago
2000
An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum num...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simu...