7 search results - page 1 / 2 » Performance Optimization of Latency Insensitive Systems Thro... |
ICCAD
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
TCAD
2008
13 years 4 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
RSP
1998
IEEE
13 years 9 months ago
1998
IEEE
One of the major differences in partitioning for codesign is in the way the communication cost is evaluated. Generally the size of the edge cut-set is used. When communication bet...
ICC
2007
IEEE
13 years 11 months ago
2007
IEEE
— The analysis regarding the impact of the single-step power control (SSPC) scheme on the system performance such as bit error rate, packet error rate and queueing variation is h...