1370 search results - page 1 / 274 » Performance analysis and optimization of latency insensitive... |
DAC
2000
ACM
14 years 5 months ago
2000
ACM
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
TCAD
2008
13 years 4 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
ICCAD
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
We consider the problem of optimizing the performance of a latency-insensitive system (LIS) where the addition of backpressure has caused throughput degradation. Previous works ha...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carlon...