33 search results - page 1 / 7 » Performance of CMOS Current Mode Full Adders |
ISMVL
1994
IEEE
13 years 8 months ago
1994
IEEE
We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a
ISMVL
1994
IEEE
13 years 8 months ago
1994
IEEE
We present the basic structure and performance of CML current mode full adders, that are used as Carry
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
JCP
2008
13 years 4 months ago
2008
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...