27 search results - page 1 / 6 » Performance simulation modeling for fast evaluation of pipel... |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
RSP
2003
IEEE
13 years 10 months ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
ASPLOS
1991
ACM
13 years 8 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
SIGMOD
2004
ACM
14 years 5 months ago
2004
ACM
We present new algorithms on commodity graphics processors to perform fast computation of several common database operations. Specifically, we consider operations such as conjunct...