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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
13 years 12 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
IPPS
2006
IEEE
14 years 7 days ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
BMCBI
2008
182views more  BMCBI 2008»
13 years 6 months ago
MiMiR - an integrated platform for microarray data sharing, mining and analysis
Background: Despite considerable efforts within the microarray community for standardising data format, content and description, microarray technologies present major challenges i...
Chris Tomlinson, Manjula Thimma, Stelios Alexandra...
WSC
1998
13 years 7 months ago
Applying Temporal Databases to HLA Data Collection and Analysis
The High Level Architecture (HLA) for distributed simulations was proposed by the Defense Modeling and Simulation Office of the Department of Defense (DOD) in order to support int...
Thom McLean, Leo Mark, Margaret L. Loper, David Ro...
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
13 years 11 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...