192 search results - page 4 / 39 » Pipelined FPGA Adders |
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
ASPDAC
2012
ACM
12 years 16 days ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
ISVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8×8-b...
ASAP
2007
IEEE
13 years 8 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...