192 search results - page 5 / 39 » Pipelined FPGA Adders |
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
FPGA
2009
ACM
14 years 2 days ago
2009
ACM
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
FPL
1997
Springer
13 years 9 months ago
1997
Springer
Abstract. Pipeline morphing is a simple but e ective technique for recon guring pipelined FPGA designs at run time. By overlapping computation and recon guration, the latency assoc...
FPGA
2001
ACM
13 years 9 months ago
2001
ACM
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...