11 search results - page 2 / 3 » Place and route considerations for voltage interpolated desi... |
GLOBECOM
2009
IEEE
14 years 3 days ago
2009
IEEE
—Most research works in routing and design of optical networks assume that the optical medium can carry data signals without any bit error. However, physical impairments of the o...
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
VLSID
2005
IEEE
13 years 11 months ago
2005
IEEE
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...