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» Power Estimation of Cell-Based CMOS Circuits
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DAC
1996
ACM
13 years 9 months ago
Power Estimation of Cell-Based CMOS Circuits
PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
Alessandro Bogliolo, Luca Benini, Bruno Ricc&ograv...
ICCAD
1994
IEEE
121views Hardware» more  ICCAD 1994»
13 years 9 months ago
A cell-based power estimation in CMOS combinational circuits
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
13 years 11 months ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
ISLPED
1995
ACM
80views Hardware» more  ISLPED 1995»
13 years 8 months ago
Techniques for fast circuit simulation applied to power estimation of CMOS circuits
We present a transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits. The proposed approach uses s...
Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. K...
TVLSI
2002
88views more  TVLSI 2002»
13 years 4 months ago
Least-square estimation of average power in digital CMOS circuits
The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this brie...
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chan...