In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This ...
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu