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FPL
2008
Springer
129views Hardware» more  FPL 2008»
13 years 6 months ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
ASPDAC
2010
ACM
124views Hardware» more  ASPDAC 2010»
13 years 3 months ago
MuCCRA-3: a low power dynamically reconfigurable processor array
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tun...
ICRA
2006
IEEE
158views Robotics» more  ICRA 2006»
13 years 11 months ago
An Agent-based Mobile Robot System using Configurable SOC Technique
– To make a mobile robot with real-time vision system adapt to the highly dynamic environments and emergencies under the real-time constraints, a significant account of processin...
Yan Meng
ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
13 years 10 months ago
Embedded reconfigurable array targeting motion estimation applications
Motion estimation is a complex computation found in video compression algorithms, such as standards like MPEG-4 and H.263. This paper proposes an embedded reconfigurable array for...
Sami Khawam, Tughrul Arslan, Fred Westall
PACS
2000
Springer
99views Hardware» more  PACS 2000»
13 years 8 months ago
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
Roberto Maro, Yu Bai, R. Iris Bahar