— This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a Power System on a Chip (PSoC). The paper wil...
Chika O. Nwankpa, A. S. Deese, Qingyan Liu, Aaron ...
This paper presents a new dynamic power management architecture of a System on Chip. The Power State Machine describing the status of the core follows the recommendations of the A...
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...