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ISCAS
2006
IEEE
100views Hardware» more  ISCAS 2006»
13 years 11 months ago
Power system on a chip (PSoC)
— This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a Power System on a Chip (PSoC). The paper wil...
Chika O. Nwankpa, A. S. Deese, Qingyan Liu, Aaron ...
CORR
2007
Springer
108views Education» more  CORR 2007»
13 years 5 months ago
SystemC Analysis of a New Dynamic Power Management Architecture
This paper presents a new dynamic power management architecture of a System on Chip. The Power State Machine describing the status of the core follows the recommendations of the A...
Massimo Conti
ISPD
1997
ACM
142views Hardware» more  ISPD 1997»
13 years 9 months ago
Minimization of chip size and power consumption of high-speed VLSI buffers
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
D. Zhou, X. Y. Liu
TCAD
2010
160views more  TCAD 2010»
13 years 1 days ago
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 3 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi