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ICCD
2000
IEEE
80views Hardware» more  ICCD 2000»
13 years 9 months ago
Power-Sensitive Multithreaded Architecture
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-...
John S. Seng, Dean M. Tullsen, George Cai
TJS
2010
145views more  TJS 2010»
12 years 11 months ago
Analyzing and enhancing the parallel sort operation on multithreaded architectures
The Sort operation is a core part of many critical applications. Despite the large efforts to parallelize it, the fact that it suffers from high data-dependencies vastly limits it...
Layali K. Rashid, Wessam Hassanein, Moustafa A. Ha...
TPDS
2010
144views more  TPDS 2010»
13 years 3 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
12 years 8 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
IPPS
2010
IEEE
13 years 2 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem