11 search results - page 2 / 3 » Precise Register Allocation for Irregular Architectures |
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
DAC
1995
ACM
13 years 9 months ago
1995
ACM
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
LCTRTS
2001
Springer
13 years 10 months ago
2001
Springer
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
LCPC
2005
Springer
13 years 11 months ago
2005
Springer
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...