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» Prediction of Power Requirements for High-Speed Circuits
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GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
14 years 1 days ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
14 years 11 days ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
DATE
2007
IEEE
138views Hardware» more  DATE 2007»
14 years 10 days ago
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
13 years 11 months ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
DAC
2002
ACM
14 years 7 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy