500 search results - page 1 / 100 » Procedure Placement Using Temporal Ordering Information |
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
CASES
2004
ACM
13 years 10 months ago
2004
ACM
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
HICSS
2003
IEEE
13 years 10 months ago
2003
IEEE
Abstract— This paper presents a framework for verifying compilation tools for parametrised hardware libraries with placement information. Such libraries are captured in Pebble, a...
CASES
2010
ACM
13 years 3 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
DAWAK
2007
Springer
13 years 9 months ago
2007
Springer
Most methods for temporal pattern mining assume that time is represented by points in a straight line starting at some initial instant. In this paper, we consider a new kind of fir...