41 search results - page 2 / 9 » Process variation aware clock tree routing |
TCAD
2008
13 years 5 months ago
2008
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
— In this paper, an efficient linear time algorithm TACO is proposed for the first time to minimize the worst case clock skew in the presence of on-chip thermal variation. TACO...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framewor...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ICCAD
2010
IEEE
13 years 3 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...