A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...