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    » Quasi-Resonant Interconnects: A Low Power Design Methodology
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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    13 years 7 months ago
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    Download  dropzone.tamu.edu
    Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
    Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
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    DAC
    1998
    ACM
    132views Computer Architecture» more  DAC 1998»
    Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques
    13 years 9 months ago
    Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques
    Download  www.kuroda.elec.keio.ac.jp
    Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishik...
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    TVLSI
    2010
    203views Artificial Intelligence» more  TVLSI 2010»
    LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
    12 years 11 months ago
    LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
    Download  www.icims.csl.uiuc.edu
    In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
    Deming Chen, Jason Cong, Yiping Fan, Lu Wan
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    ASPDAC
    2011
    ACM
    167views Hardware» more  ASPDAC 2011»
    Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
    12 years 8 months ago
    Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
    Download  web.ics.purdue.edu
    - In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
    Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaus...
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    ISCAS
    2006
    IEEE
    108views Hardware» more  ISCAS 2006»
    Design methodology for global resonant H-tree clock distribution networks
    13 years 11 months ago
    Design methodology for global resonant H-tree clock distribution networks
    Download  www.ece.rochester.edu
    Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
    Jonathan Rosenfeld, Eby G. Friedman
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