214 search results - page 3 / 43 » Quasi-Resonant Interconnects: A Low Power Design Methodology |
SLIP
2009
ACM
13 years 12 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
ASAP
2010
IEEE
13 years 6 months ago
2010
IEEE
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication ...
TVLSI
2008
13 years 5 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
SLIP
2004
ACM
13 years 10 months ago
2004
ACM