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» RC Interconnect Optimization Under the Elmore Delay Model
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DAC
1994
ACM
13 years 10 months ago
RC Interconnect Optimization Under the Elmore Delay Model
An e cient solution to the wire sizing problem WSP usingthe Elmoredelaymodelisproposed. Two formulations of the problem are put forth: in the rst, the minimum interconnect delay i...
Sachin S. Sapatnekar
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 10 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
DATE
2007
IEEE
96views Hardware» more  DATE 2007»
14 years 3 days ago
Self-heating-aware optimal wire sizing under Elmore delay model
Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal e ects impact a...
Min Ni, Seda Ogrenci Memik
ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
14 years 2 months ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...
ICCAD
1996
IEEE
122views Hardware» more  ICCAD 1996»
13 years 10 months ago
Analytical delay models for VLSI interconnects under ramp input
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu