Sciweavers

17 search results - page 1 / 4
» Realizable reduction for RC interconnect circuits
Sort
View
ICCAD
1999
IEEE
67views Hardware» more  ICCAD 1999»
13 years 10 months ago
Realizable reduction for RC interconnect circuits
Interconnect reduction is an important step in the design and analysis of complex interconnects found in present-day integrated circuits. This paper presents techniques for obtain...
Anirudh Devgan, Peter R. O'Brien
ICCAD
1995
IEEE
108views Hardware» more  ICCAD 1995»
13 years 9 months ago
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
Haifang Liao, Wayne Wei-Ming Dai
DATE
2004
IEEE
106views Hardware» more  DATE 2004»
13 years 9 months ago
Realizable Reduction for Electromagnetically Coupled RLMC Interconnects
This paper presents a realizable RLMC1 reduction algorithm for extracted interconnect circuits based on two effective approaches: RL branch reduction and RC/LC node reduction. Our...
Rong Jiang, Charlie Chung-Ping Chen
DAC
1995
ACM
13 years 9 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
13 years 7 months ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan