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» Recovery Mechanisms for Dual Core Architectures
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DFT
2006
IEEE
74views VLSI» more  DFT 2006»
13 years 10 months ago
Recovery Mechanisms for Dual Core Architectures
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic informa...
Christian El Salloum, Andreas Steininger, Peter Tu...
FAST
2008
13 years 5 months ago
Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling
In this paper we develop a recovery conscious framework for multi-core architectures and a suite of techniques for improving the resiliency and recovery efficiency of highly conc...
Sangeetha Seshadri, Lawrence Chiu, Cornel Constant...
ICPP
2008
IEEE
13 years 11 months ago
Enabling Streaming Remoting on Embedded Dual-Core Processors
Dual-core processors (and, to an extent, multicore processors) have been adopted in recent years to provide platforms that satisfy the performance requirements of popular multimed...
Kun-Yuan Hsieh, Yen-Chih Liu, Po-Wen Wu, Shou-Wei ...
DATE
2004
IEEE
131views Hardware» more  DATE 2004»
13 years 8 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
DAC
2011
ACM
12 years 4 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...