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» Reducing the Complexity of ILP Formulations for Synthesis
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ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
13 years 9 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
13 years 11 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
ETS
2009
IEEE
117views Hardware» more  ETS 2009»
13 years 2 months ago
A Two Phase Approach for Minimal Diagnostic Test Set Generation
We optimize the full-response diagnostic fault dictionary from a given test set. The smallest set of vectors is selected without loss of diagnostic resolution of the given test se...
Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
DDECS
2009
IEEE
202views Hardware» more  DDECS 2009»
13 years 11 months ago
Asynchronous two-level logic of reduced cost
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
Igor Lemberski, Petr Fiser
ICCD
2007
IEEE
179views Hardware» more  ICCD 2007»
14 years 1 months ago
Energy-aware co-processor selection for embedded processors on FPGAs
In this paper, we present co-processor selection problem for minimum energy consumption in hw/sw co-design on FPGAs with dual power mode. We provide theoretical analysis for the p...
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Suda...