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ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
13 years 10 months ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
13 years 10 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...
IPPS
2007
IEEE
13 years 11 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
DAC
1996
ACM
13 years 8 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl