Sciweavers

12 search results - page 1 / 3
» Reliability aware through silicon via planning for 3D stacke...
Sort
View
DATE
2009
IEEE
154views Hardware» more  DATE 2009»
13 years 11 months ago
Reliability aware through silicon via planning for 3D stacked ICs
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kua...
SLIP
2009
ACM
13 years 11 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
ICCAD
2009
IEEE
129views Hardware» more  ICCAD 2009»
13 years 2 months ago
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 2 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
DATE
2009
IEEE
161views Hardware» more  DATE 2009»
13 years 11 months ago
Co-design of signal, power, and thermal distribution networks for 3D ICs
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...
Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad ...