133 search results - page 1 / 27 » Resilient design in scaled CMOS for energy efficiency |
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
ISLPED
2010
ACM
13 years 5 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Future system design methodologies must accept the fact that the underlying hardware will be imperfect, and enable design of robust systems that are resilient to hardware imperfec...
ECCTD
2011
12 years 5 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...