70 search results - page 4 / 14 » Retargetable Cache Simulation Using High Level Processor Mod... |
CODES
2009
IEEE
14 years 17 days ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
MTA
2006
13 years 5 months ago
2006
Abstract There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is a...
AINA
2007
IEEE
14 years 5 days ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
ISVLSI
2007
IEEE
14 years 3 days ago
2007
IEEE
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
ISPASS
2007
IEEE
14 years 3 days ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...