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» Retention-Aware Test Scheduling for BISTed Embedded SRAMs
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ETS
2006
IEEE
93views Hardware» more  ETS 2006»
10 years 4 months ago
Retention-Aware Test Scheduling for BISTed Embedded SRAMs
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
Qiang Xu, Baosheng Wang, F. Y. Young
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
10 years 2 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...
CSREAESA
2008
9 years 12 months ago
BIST-BASED Group Testing for Diagnosis of Embedded FPGA Cores
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
Alireza Sarvi, Carthik A. Sharma, Ronald F. DeMara
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
10 years 3 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
DATE
2005
IEEE
160views Hardware» more  DATE 2005»
10 years 4 months ago
SOC Testing Methodology and Practice
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction...
Cheng-Wen Wu
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