7 search results - page 1 / 2 » Retention-Aware Test Scheduling for BISTed Embedded SRAMs |
ETS
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
CSREAESA
2008
13 years 6 months ago
2008
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
MTDT
2003
IEEE
13 years 9 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction...