60 search results - page 4 / 12 » Retiming with Interconnect and Gate Delay |
ICCAD
2000
IEEE
13 years 10 months ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
VLSISP
2008
13 years 5 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...