14 search results - page 3 / 3 » SAT-based ATPG for Path Delay Faults in Sequential Circuits |
DAC
1994
ACM
13 years 8 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...