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ISQED
2006
IEEE
153views Hardware» more  ISQED 2006»
13 years 10 months ago
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
Chong Zhao, Sujit Dey
ASYNC
2005
IEEE
90views Hardware» more  ASYNC 2005»
13 years 10 months ago
SEU-Tolerant QDI Circuits
This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circu...
Wonjin Jang, Alain J. Martin
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
13 years 10 months ago
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a ...
G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, F...
VLSI
2005
Springer
13 years 10 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...