175 search results - page 3 / 35 » SOC Testing Methodology and Practice |
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...
ICCD
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...